The present invention relates generally to mechanisms for recording events that occur during clock switching, and more particularly to semiconductor devices that register interrupting events for synchronous systems including multiple clocked domains where a particular clock may be temporarily absent.
Within a single computing system, a number of different components or subsystems may operate at different frequencies. In particular, various components or subsystems utilized for the construction of a computing system may independently operate at different frequencies, such as in microprocessors and microcontrollers, where certain components or subsystems have a faster rate of operation than the operating frequencies of other system components or subsystems. Therefore, typically, it is desirable to devise computing systems with the ability to support multiple domains, which may operate at different frequencies.
For instance, most computing systems typically include a number of electronic circuits referred to as “clocked logic domains” that operate independently based on electrical “timing” or “clock” signals. Such clock signals are used to control and coordinate the activities of the computing system's various components or subsystems. One of the clock signals, the system clock signal, is a reference clock signal to which the various components or subsystems of the computer synchronize their operation. The computing system's components or subsystems generally include device clock synthesizer to generate a device clock signal synchronized to the system clock signal.
A synchronously operable semiconductor device, such as a particular device interface, or bus operating at a specific frequency, may define a distinct clocked logic domain. However, fabrication of semiconductor devices having processors has introduced new timing problems for device manufacturers. Registration of interrupting events, particularly between various clocked logic domains presents a number of challenges to the designers and manufacturers of these computing systems. For example, a variety of computing devices, such as hand-held personal digital assistants (PDAs) or wireless devices including mobile phones or a mobile computers (a hand-held computer, palm top computer or notebook computer, as examples) may have at least one mode, such as a sleep mode, to conserve power when the computing device is not currently being used.
Using an interrupt recording mechanism, an event (e.g., an interrupting event, or a transition to a particular mode) may be recorded. However, a synchronous system that needs to register interrupting events that may occur during clock switching may not be maintained fully synchronous because of the asynchronous nature of such interrupting events. For example, during an interrupting event when a specific clock or the clocks to a particular portion or portions of the synchronous system may be turned off, denied, or absent, an event capture mechanism may record the interrupting event asynchronously. Thus, such arrangement, or mechanism for recording the interrupting event may be inadequate for a fully synchronous system, as the synchronous system may be rendered asynchronous in part by the occurrence of the interrupting event.
Accordingly, such technique may be unable to appropriately capture interrupting events across multiple independently clocked logic domains while maintaining a system fully synchronous. Furthermore, absent appropriate interrupt recording mechanism, such approach may create problems in the validation stage of a circuit design including multiple asynchronous circuit regions that may be independently clocked. As a result, a fully synchronous system may not be feasible because such mechanism may be unable to register interrupting events that may occur during data transfer across independently clocked multiple domains where some logic is denied a clock.
Therefore, it is desirable to synchronously record interrupting events.